[Verilog]同步FIFO案例 --- 参数化的module

                         同步FIFO案例 --- 参数化的module

一、同步FIFO设计要点

二、同步FIFO范例

module cm_slv_dec_sync_fifo #(parameter    FIO_DATA_WIDTH = 32'd32,parameter    FIO_DATA_WIDTH = 32'd32
) (input                                fifo_rstb,input                                fifo_clk,//write clock domaininput                                fifo_wr_req,input  [FIFO_DATA_WIDTH-1:0]         fifo_wr_data,output                               fifo_wr_ack,//read clock domainoutput                               fifo_rd_req,output  [FIFO_DATA_WIDTH-1:0]        fifo_rd_data,input                                fifo_rd_ack,
)localparam FIFO_PTR_BIT = clog2(FIFO_DATA_DEPTH);integer j;reg [FIFO_DATA_WIDTH-1:0]              fifo_mem[FIFO_DATA_DEPTH-1:0];
reg [FIFO_PTR_BIT:0]                   wr_ptr;
reg [FIFO_PTR_BIT:0]                   rd_ptr;write